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NEC first with hafnium for low-standby ICs

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NEC first with hafnium for low-standby ICs

Posted on: 19-Jan-2007

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NEC Electronics deserves a tip of the hat for apparently being the first company to incorporate a hafnium-based gate dielectric into low-standby-power (LSTP) cell-based ICs. At last June’s 2006 Symposium on VLSI Technology in Honolulu, NEC presented the 55-nm LSTP technology, but no one was 100 percent sure that the company would go ahead with the hafnium-based dielectric in production.

NEC followed through, announcing Thursday (Jan. 18th) that it is accepting orders for cell-based ICs using 55-nm design rules and a hafnium-silicon-oxygen-nitrogen (HfSiON) mix as the gate dielectric. Libraries will be ready in March, aimed at cell phone ICs, digital still and video cameras chipsets, and other battery-operated markets.

The gate stack stops short of switching to metal gate electrodes, using conventional doped polysilicon electrodes. The HfSiON probably has a k-value in the low-to-mid-teens, perhaps double the dielectric constant of the nitrided oxides now widely used. That makes this more of a “mid-k” rather than a true high-k dielectric, though the glass-like film created when a metallic element such as hafnium is introduced is much different than today’s nitrided oxides.

Masao Fukuma, senior vice president of R&D at NEC Electronics, said NEC uses conventional deposition techniques, rather than the more expensive atomic-level deposition (ALD), for the dielectric deposition.

Low standby power chips are a different breed of cat from high-performance logic. The threshold voltage for LSTP CMOS transistors must be set high – at 1.2 V for the NEC 55-nm process. To keep the subthreshold leakage under control, conventional CMOS requires relatively high dopant concentrations in the channel. However, that degrades mobilities and junction leakage.

To increase the threshold voltage, NEC’s approach takes advantage of the Fermi-level pinning phenomenon seen when high-k dielectrics and polysilicon electrodes are combined. By using a HfSiON gate dielectric to control the gate work function without increasing dopant concentrations, NEC achieves perhaps 20 percent higher mobilities as well as reduced gate leakage.

For those of you who crave specs, NEC is claiming an EOT (electrical or effective oxide thickness) of 1.85. The transistors have drive currents of 525/295 microAmperes for n- and pMOS, at 20 picoAmperes in the off-state, and rev up to an Ion of 780/400 microamperes at an Ioff of 3 nanoAmperes with a supply voltage of 1.2 V. The line and space at the first metal layer are 80/80 nanometers, delivering an SRAM cell size of 0.432 micrometer squared.

 

Bohr still likes Intel’s “dry” lithography decision for 45 nanometers

 

The competition between Intel and the IBM/AMD partnership includes an well-known but still interesting contrast at the 45-nm node, lithographically speaking. IBM and AMD will adopt immersion scanners for critical layers, while Intel will use “dry” 193-nm scanners.

The common wisdom is that Intel chose to stick with dry scanners because of its schedule: it finalized its 45-nm process in 2005, before immersion was known to be usable. Intel had its 45-nm test chip ready by January 2006, and the company announced this week that its 45-nm Penryn processor design is complete. IBM and AMD were able to go with immersion because their schedule is somewhat behind Intel’s – perhaps six months.

Mark Bohr, director of Intel’s process architecture, said “even if we took our 45-nm process and delayed it a year, we wouldn’t change our minds” about immersion.

Intel will use immersion scanners at the 32-nm node, he said. If Intel had to make its “dry or wet” decision for the 45-nm node all over again, the company would stick with dry, he said.

For one mask level of its 45-nm process, the critical gate layer, Intel uses double patterning. Bohr said double patterning “gives us a nice square edge at the gate layer, which improves the gate-to-gate spacing.” Photos of gates from competing processor vendors formed with immersion scanners, he said, show “roundings, which are dangerous.”

The square edge obtained with double patterning at the gate-formation layer is “worth the extra cost” involved with double patterning, he said.

Intel also uses alternating phase shift masks at the 45-nm node, but that hard shifting technique is of little benefit at the gate layer, he said.

IBM and AMD are touting immersion as an advantage over Intel at the 45-nm node. At the International Electron Devices Meeting (IEDM) in San Francisco last month, Nick Kepler, vice president of logic technology development at AMD, said AMD “will be getting there first” with immersion lithography, buying wet tools for its new fab in Dresden, Germany.

For AMD’s 45-nm process “there is no double patterning, which helps both our design and, within the fab, keeps our throughput higher,” Kepler said.

The biggest advantage is improved pattern corner roundings and gate-to-tip distance, Kepler said.  Paul Agnello, the 45-nm program manager at IBM, added that immersion lithography helps ease the need for restrictive design rules, giving designers a bit more freedom than if dry lithography was employed.

Defects continue to be a source of conflicting reports. Kepler and Agnello said that by getting early access to a pre-production ASML 1200i immersion scanner at the Albany research center, IBM and AMD were able to wring defects out of their 45-nm process. The partners showed a simple bar chart at IEDM, with relatively high defect levels early in the development process, and essentially equivalent defect levels for dry and immersion scanners for the optimized 45-nm process.

Other technology managers are saying that immersion still results in higher defect levels. A TSMC research manager at IEDM said that if dry scanners and immersion scanners are compared today, defect rates are about 10 times higher for immersion.

In a speech at SEMI’s SII conference earlier this month in Half Moon Bay, Calif., Hans Stork, senior vice president at Texas Instruments, referred to continuing challenges in reducing immersion-related defects, as well as improving throughput and alignment. Those challenges are part of the normal development process, and immersion will be ready for insertion when TI ramps up its 45-nm process, he said.

Cost remains a concern as well. Venu Menon, a Texas Instruments vice president, said at an Applied Materials panel during IEDM that immersion tools are “north of $50 million.”

 

 

Mears LLC claims “superlattice” is a knob worth turning

 

Companies large and small try to entice customers to pay for their new technologies, without giving away their proprietary knowledge to competitors.

In that sense, Mears LLC, is in good company. After all, any company that bases its livelihood solely on its intellectual property (IP) must be particularly careful about how it discloses its secret sauce.

Mears is making fairly large claims, i.e., that it is has developed a way to reduce gate leakage by 60 to 80 percent by introducing a “superlattice” to the channel. At the same time, it is being fairly secretive about exactly how it achieves such dramatic gains.

Bob Mears has credentials: he taught electronic engineering at Cambridge University, where he came up with ideas about how to re-engineer the silicon bandgap by epitaxially depositing silicon in the channel region. Since 2001 he has been working to turn his ideas into a licensable IP package.

The Mears Silicon Technology introduces an epitaxial step inserted into a standard CMOS flow, prior to the gate formation. The 15-person company, based in Waltham, Mass., has worked with the Advanced Technology Development Fab (ATDF), the contract fab subsidiary of Sematech in Austin, running more than a thousand test wafers. Mears also contracted with epi specialist Lawrence Semiconductor Research Laboratory, Inc. during the development process. Mears also worked with ASM International, using its Epsilon deposition tool. That is significant in that no proprietary tooling is needed. ASM’s Epsilon is the same tool that Mears’ customers will use to create the superlattice.

Mears said the MST silicon is deposited by a proprietary recipe, creating a laminate about 100 Angstroms thick which is more two-dimensional than a conventional epitaxial silicon recipe. While this superlattice is still a single crystal, the atomic planes are slightly stepped off from each other in sheets, like graphite.

Mears claims this does two things: in the horizontal or lateral plane it reduces the effective mass and improves the mobility. In the vertical direction mobility is inhibited, because the effective mass is made higher, making it harder for electrons and holes to travel in the vertical direction through the proprietary epitaxial  layer. And that, Mears claims, has a direct bearing on gate leakage.

“The various tunneling mechanisms that result in gate leakage all have an impedance matching condition as carriers go across the junction. By making the effective mass higher in the superlattice, a mismatch occurs which is like an impedance match. This mismatch can reduce the leakage in the vertical direction and enhance the drive current through the channel,” he said.

What about defects?

“Everybody wants to know about defectivity,” Mears acknowledged. “We have put the wafers through the standard defect measurements, and we don’t see the same sort of defects that we see with strained silicon,” he said.

Are there parallels with strained silicon? That’s what makes this company so enticing. If Mears has come up with something half as important as strained silicon, the chip industry needs to carefully check out this company’s claims. Read United States Patent Application 0060273299 and let me know, please, if you think Mears is turning an important knob. I’m at dlammers@vlsiresearch.com.

 

Top Scaling Challenges for 2007

 

Productivity

Maintaining the historical 25 percent per annum reduction in cost-per-function is the metric the chip industry can be most proud of. However, productivity is being challenged as never before.

Masao Fukuma, senior vice president of research and development at NEC Electronics, makes the point that SoC vendors are under the most cost pressure. SoCs often have relatively low volumes compared with microprocessors, DRAMs, and flash memories. MPU and memory vendors can use lithographic double patterning and, eventually, Extreme Ultraviolet (EUV) lithography. Those techniques may be too expensive for many consumer-use chips, Fukuma said.

 High-k

 Hafnium-based oxides with metal gates could blast through the scaling barriers of nitrided oxides (SiON). But challenges remain, including finding a metal that delivers the right work function for the PFET electrode and keeping the threshold voltages stable.

Ghavam Shahidi, director of silicon technology at IBM’s T.J. Watson research center (Yorktown Heights, N.Y.), said a high-k solution would improve performance somewhat. On power, however, hopes for high-k may be too high. A relatively small portion of overall leakage current is through the gate oxide, with substrate leakage as the larger component. So high-k may not have a major impact on power.

Where high-k will have a major impact, Shahidi said, is in scaling the length of the poly, making more room for the contacts, and getting the industry back on track in terms of gate size reductions.  

 Immersion lithography

 IBM and its process development partner AMD claim defect levels already are equivalent for both dry and immersion lithography. Others concede defects are several times higher for immersion at this point.

Immersion has hidden benefits: Paul Agnello, project manager for 45-nm SOI device and integration at IBM, said fewer design restrictions are required when immersion tools are used.

The tool vendors have done their part, meeting schedules for production-worthy scanner shipments despite worries last year that schedules would slip. That will help IBM and AMD bring up their 45-nm processes just 18 months after the 65-nm generation, said Nick Kepler, vice president of logic technology development at AMD.

Immersion’s track record bodes well for improving “wet” lithographic productivity in 2007 and beyond.

Ultra low-k dielectrics

 For the 45-nm node, IBM and AMD will reduce the dielectric constant for the global routing layers (M4-M6) to 2.4, with other layers at 2.7. IBM’s Agnello said the partners have figured out how to avoid etch stop and capping layers, using a unique pre-cursor.

While IBM and AMD claim their reliability data is “rock solid,” the industry overall still has psychic scars from the relatively weak mechanical strength of the low-k-enhanced interconnect layers first used at the 90-nm node.

NEC also is optimistic about low-k progress. Yasunori Mochizuki, chief research manager at NEC’s system devices research laboratories (Sagamihara, Japan), said NEC was able to integrate porous low-k dielectrics at the 65-nm node, keeping moisture out of the pores. Going forward, NEC and Tosoh Corp.’s electronic materials division have developed two pre-cursors that eliminate the need for an etch stop layer. The result, Mochizuki said, is a three orders of magnitude reduction in defects.

 Enhancing strain

Intel has been doing strained silicon for so long by embedding silicon germanium at the source and drain of the PFET that it would easy to assume that this eSiGe technique is used widely throughout the industry. In fact, embedded SiGe is only now being adopted, at the 65-nm node by IBM and AMD, and by Texas Instruments for its high-performance 65-nm process that it uses to make Sun’s microprocessors (but not for TI’s DSPs). Freescale Semiconductor, for example, will adopt eSiGe for its high-performance 45-nm node “after our other strain techniques run out of steam” said Suresh Venkatesan, senior director of CMOS platform device development at Freescale Semiconductor Inc.

As the space to deposit the silicon germanium becomes smaller as scaling proceeds, companies may turn to silicon carbon as a strain technique for the NFETs. But it remains unclear whether the performance gain from SiC is worth the additional complexity. Scott Thompson, a professor at the University of Florida who implemented strain while managing Intel’s 90-nm process development effort, is an optimist. “There is plenty of room to get higher mobilities with strain techniques. We can get another two generations at the PMOS,” Thompson said at the International Electron Devices Meeting in mid-December.

 

 

 

 

 

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