The First Thing
The first thing a new Web site needs is a problem that needs solving. We feel the industry needs a place to publish technical information quickly, in a form which can be quickly found on the World Wide Web.
Think about how things work today. Technical papers at a major technical conference must be prepared and submitted for acceptance at least six months in advance. That is a third of a node, too long in today’s fast-moving semiconductor industry.
WeSRCH.com offers a complement to the major technical conferences. Go to WeSRCH.com, sign up and log in, then upload the paper and supporting graphics. Moments later, the paper is out there on the Web, searchable and one-click-addressable. The papers can be read for free. No pay-per-view fees, or memberships to technical databases.
WeSRCH.com also enables feedback in the form of reader commentaries and ratings. And experts can form communities of like-minded technologists facing similar challenges. The communities can be public: open to all comers. Or the communities can be private: password-protected, with membership limited by the moderators.
WeSRCH.com is a powerful tool for the technical community. You are welcome to participate. We welcome your feedback.
Top Scaling Challenges for 2007
Maintaining the historical 25 percent per annum reduction in cost-per-function is the metric the chip industry can be most proud of. However, productivity is being challenged as never before.
Masao Fukuma, senior vice president of research and development at NEC Electronics, makes the point that SoC vendors are under the most cost pressure. SoCs often have relatively low volumes compared with microprocessors, DRAMs, and flash memories. MPU and memory vendors can use lithographic double patterning and, eventually, Extreme Ultraviolet (EUV) lithography. Those techniques may be too expensive for many consumer-use chips, Fukuma said.
Hafnium-based oxides with metal gates could blast through the scaling barriers of nitrided oxides (SiON). But challenges remain, including finding a metal that delivers the right work function for the PFET electrode and keeping the threshold voltages stable.
Ghavam Shahidi, director of silicon technology at IBM’s T.J. Watson research center (Yorktown Heights, N.Y.), said a high-k solution would improve performance somewhat. On power, however, hopes for high-k may be too high. A relatively small portion of overall leakage current is through the gate oxide, with substrate leakage as the larger component. So high-k may not have a major impact on power.
Where high-k will have a major impact, Shahidi said, is in scaling the length of the poly, making more room for the contacts, and getting the industry back on track in terms of gate size reductions.
IBM and its process development partner AMD claim defect levels already are equivalent for both dry and immersion lithography. Others concede defects are several times higher for immersion at this point.
Immersion has hidden benefits: Paul Agnello, project manager for 45-nm SOI device and integration at IBM, said fewer design restrictions are required when immersion tools are used.
The tool vendors have done their part, meeting schedules for production-worthy scanner shipments despite worries last year that schedules would slip. That will help IBM and AMD bring up their 45-nm processes just 18 months after the 65-nm generation, said Nick Kepler, vice president of logic technology development at AMD.
Immersion’s track record bodes well for improving “wet” lithographic productivity in 2007 and beyond.
Ultra low-k dielectrics
For the 45-nm node, IBM and AMD will reduce the dielectric constant for the global routing layers (M4-M6) to 2.4, with other layers at 2.7. IBM’s Agnello said the partners have figured out how to avoid etch stop and capping layers, using a unique pre-cursor.
While IBM and AMD claim their reliability data is “rock solid,” the industry overall still has psychic scars from the relatively weak mechanical strength of the low-k-enhanced interconnect layers first used at the 90-nm node.
NEC also is optimistic about low-k progress. Yasunori Mochizuki, chief research manager at NEC’s system devices research laboratories (Sagamihara, Japan), said NEC was able to integrate porous low-k dielectrics at the 65-nm node, keeping moisture out of the pores. Going forward, NEC and Tosoh Corp.’s electronic materials division have developed two pre-cursors that eliminate the need for an etch stop layer. The result, Mochizuki said, is a three orders of magnitude reduction in defects.
Intel has been doing strained silicon for so long by embedding silicon germanium at the source and drain of the PFET that it would easy to assume that this eSiGe technique is used widely throughout the industry. In fact, embedded SiGe is only now being adopted, at the 65-nm node by IBM and AMD, and by Texas Instruments for its high-performance 65-nm process that it uses to make Sun’s microprocessors (but not for TI’s DSPs). Freescale Semiconductor, for example, will adopt eSiGe for its high-performance 45-nm node “after our other strain techniques run out of steam” said Suresh Venkatesan, senior director of CMOS platform device development at Freescale.
As the space to deposit the silicon germanium becomes smaller as scaling proceeds, companies may turn to silicon carbon as a strain technique for the NFETs. But it remains unclear whether the performance gain from SiC is worth the additional complexity. Scott Thompson, a professor at the University of Florida who implemented strain while managing Intel’s 90-nm process development effort, is an optimist. “There is plenty of room to get higher mobilities with strain techniques. We can get another two generations at the PMOS,” Thompson said at the International Electron Devices Meeting in mid-December.