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Memory Controller and PHY Support Multiple DDR Standards While Reducing Latency and Standby Power
Synopsys' new DesignWare® DDR4 Memory Interface IP supports DDR4, DDR3, and LPDDR2/3 in a single core, enabling designers to interface with either high-performance or low-power SDRAMs in the same SoC. The new DDR4 IP supports all key DDR4 features planned for the upcoming JEDEC standard and includes:
- A 13% increase in raw bandwidth
- Up to a 50% reduction in overall latency
- New low-power features that provide intelligent system monitoring and control to power down elements of the IP
- Real-time scheduling features in the unique CAM-based DDR controller that maximizes performance and minimizes latency
See how you can future-proof your designs with DesignWare DDR4 IP:
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