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January 2008

:: Event Highlights from The ConFab

High-level semiconductor manufacturing executives from around the world are among those presenting at The ConFab this year from May 18 -21, 2008 at Loews Lake Las Vegas Resort in
Las Vegas, Nevada.

:::Confirmed Speakers To Date Include:

  • Ben Suh, VP ASIC/Foundry Business Development, Samsung
  • Kazuo Ushida, President, Nikon Precision
  • Masaaki Kinugawa, Technology Executive, SoC, Toshiba
  • Sitaram Akalgud, Director, 3D Interconnect, SEMATECH

:::The conference sessions include:

  • The Next Generation Factory
  • Economic Implications of 3D: Circuitry & Advanced Packaging
  • Next Generation Lithography
  • Fab Lite: Is The IDM an Endangered Species?
  • Reducing Environmental/Energy Costs

:::The ConFab is a global conference and business meeting where executives from semiconductor equipment and material suppliers meet with key decision makers from semiconductor manufacturers.

Last year, a group of the most important senior executives in the semiconductor industry from over 38 chipmakers and 30 suppliers attended The ConFab. They traveled from every corner of the globe - Asia, the U.S., and Europe - to participate in this exclusive, invitation-only event. At The ConFab, they participated in a one-of-a-kind combination of business meetings and conference sessions. All agreed that the opportunity to network with their peers in a relaxed, open atmosphere proved to be a highly worthwhile experience.

:::Who Attended The ConFab

Attendees from over 38 chipmakers participated.

  • 100% of attendees were involved in buying equipment
    for fabs.
  • Collectively, they represented over $46 billion of buying power in fab equipment over the next two years.
  • 89% were at the director level or above.
If you would like to know more about our list of participants for the 2007 event or want to become a sponsor of
The ConFab in 2008, please call Jay Novack at 603.891.9186 or please email Jay at jayn@pennwell.com
.

:: The Latest From

Solid State Technology's WaferNEWS - www.wafernews.com
Including content from SST's Semiconductor Weekly

::: Toshiba, NEC prep for 32nm -- without Fujitsu

Toshiba and NEC Electronics say they will extend their work on 45nm process technology to collaborate on developing 32nm system LSIs, in order to continue to speed up development and share cost burdens.Full story...

::: TSMC reports 32nm SRAM, sans HK+MG

Top global foundry TSMC says it has developed a 2Mb SRAM test chip with 32nm process technologies that supports both analog and digital functionality -- and doesn't rely upon high-k gate dielectrics or metal gates. The foundry also said it has made a 0.15-sq. micron high-density SRAM cell using 193nm immersion lithography with double patterning. Full story...

::: IBM: We've made 32nm high-k "gate first" SRAMs

IBM says it has fabricated 32nm chips using a high-k/metal gate (gate-first) process in SRAM chips, which it says shrinks the chips size by up to 50%, and saves about 45% total power. The technology is expected to be available in 2H09. Full story...

::: NEC details 40nm eDRAMs

NEC Electronics and its US and German subsidiaries have debuted two versions of 40nm system-on-chip devices with embedded DRAM, incorporating the same high-k dielectric features in its 55nm devices developed last fall. Full story...

:: Reports

::: Report: TSMC prepping AMD chips for 1H08

A pair of reports from Wall Street analysts suggest Taiwan foundry TSMC will begin production for some AMD microprocessors as soon as 1H08. Full story...

::: Report: Intel's 45nm line causing overseas substrate spike

The launch of Intel's new 45nm-based Penryn processors means more business from IC substrate makers with small volume production of new flip-chip substrate makers, causing several Taiwan and Japanese firms to project a 25% increase in their business next year, according to a Digitimes report. Full story...