Mainstream NAND Flash Memory is Approaching its Scaling Limitation

Mainstream NAND Flash Memory is Approaching its Scaling Limitation

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Description: Materials for Next Generation phase Change Memories, Non Volatile Memories Status, The phase Change Memories, Non Volatile Memory Market, NANA FLASH Vs. DRAM, Stand Alone NVM TAM Expansion, Flash Cell Scaling Challenges, Key Requirements of an Alternative NVM.

 
Author: Mauro Alessandri and Roberto Bez (Fellow) | Visits: 2252 | Page Views: 4785
Domain:  High Tech Category: Semiconductors Subcategory: Memory 
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Contents:
Materials for Next Generation Phase Change Memories
Mauro ALESSANDRI, Roberto BEZ
Process R&D Agrate Brianza (Milan), Italy

11 September 2011

�2011 Micron Technology, Inc.

|

1

Outline
� Non Volatile Memories Status

� The Phase Change Memories

� The Future

11 September 2011

�2011 Micron Technology, Inc.

|

2

Non Volatile Memory Market
100 1000

Total Volume (Eb)

In the last years volume of NVM increased exponentially (with a clear cost reduction..)

1

10

0.1

1

0.01 2000 2002 2004 2006 2008 2010

0.1

Year
NAND Eb DRAM Eb NAND $/Gb DRAM $/Gb

This triggered the use of NVM in a wide spectrum of applications

Intel-Micron 64Gbit NAND 20nm NAND MLC technology
11 September 2011 �2011 Micron Technology, Inc. | 3

Price ($/Gb)

10

100

NAND Flash vs. DRAM
100 1000

Total Volume (Eb)

1

10

0.1

1

0.01 2000 2002 2004 2006 2008 2010

0.1

Year
NAND Eb DRAM Eb NAND $/Gb DRAM $/Gb

Price ($/Gb)
| 4

10

100

11 September 2011

�2011 Micron Technology, Inc.

Stand-Alone NVM TAM Expansion
($K)
30,000

25,000

Wireless
20,000

15,000

SSD
Industrial / CE

}
}

Cost, Reliability, & Performance

10,000

5,000

Bulk NAND

Cost, Cost & Cost!!!

0 2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

Source: iSuppli Application Market Forecast Tool , June 2010

11 September 2011

�2011 Micron Technology, Inc.

|

5

Flash Cell Scaling Challenges
NOR Cell basic structure unchanged through the different generations
y-pitch

NAND

L W
x-pitch

Cell area scaling through:
1. Active device scaling (W/L) 2. Passive elements scaling

y-pitch

L W
x-pitch

Main scaling issues:
Number of stored electrons Cell proximity interference Tunnel and interpoly dielectric thickness Isolation spacing and WL voltage increase Random Telegraph Noise Trapping/detrapping, SILC Retention after cycling

CG CONO CFG FG CTUN

11 September 2011

�2011 Micron Technology, Inc.

|

6

Key Requirements of an Alternative NVM
� Readiness for beyond leading edge technology node � Scalability � Cost structure


MLC capable 3D stackable

� Performance


High Program and Read Throughput Low power Flexibility

� Reliability


Non-volatility with long retention (e.g. > 10 years) Extended number of read cycles High program endurance
7

11 September 2011

�2011 Micron Technology, Inc.

|

The Most Interesting...
Flash
Cell type Cell size (F2) Endurance write/read Read time Write time (byte) Erase time (byte) Scalability Scalability limits Multi-bit capability 3D Potential Relative Cost x bit Maturity No Medium 60ns (random) 1ms 1s/sector Poor NOR 10 104/ ~50us (latency)
200ms/page

STT-MRAM
NAND 5 1T/1R 4-10 >1014/ 30ns 30ns 30ns Fair Current Density/ Domain stability No Yes Low No High Very Low (development)

RRAM
1T/1R 4-5 >108/ 50ns 10ns 10ns Good Filament Yes Yes Low Very Low (development)

PCM
1T/1R 4-5 >108/ 50ns ~10ns 100ns Good Litho Yes Yes Medium Medium (samples @ 45nm)

2ms/block Fair

Tunnel oxide, HV Yes

Very high Very high (prod @ 45nm) (prod @ 25nm)

11 September 2011

�2011 Micron Technology, Inc.

|

8

Outline
� Non Volatile Memories Status

� The Phase Change Memories

� The Future

11 September 2011

�2011 Micron Technology, Inc.

|

9

Phase Change Memory Concept

Storing mechanism � amorphous / poly-crystal phases of a chalcogenide alloy, usually Ge2Sb2Te5 (GST) Sensing mechanism � resistance change of the GST Writing mechanism � self-heating due to current flow (Joule effect) Cell structure � 1 transistor, 1 resistor (1T/1R)
11 September 2011

Amorphous

Crystalline

High resistivity Low resistivity

� �

I V
Temperature



T m Tx

Reset (amorphization) Set (crystallization)

Time
�2011 Micron Technology, Inc. | 10

History of PCM Development
S. Lai and T. Lowrey, IEDM 2001 180nm F. Pellizzer et al., VLSI 2004 180nm F. Pellizzer et al., VLSI 2006 90nm G. Servalli, IEDM 2009 45nm

PCM cell

M. Gill et al., ISSCC 2002 180nm

G. Casagrande et al., VLSI 2004 180nm

Bedeschi et al., ISSCC 2008 90nm 128Mb (256Mb MLC)

C. Villa et al., ISSCC 2010 45nm 1Gb

PCM array & chip

2001

2003

2005

2007

2009

2011

Concept Demonstration
11 September 2011

Technology Validation Product Reliability

Manufacturing

�2011 Micron Technology, Inc.

|

11

Phase Change Memory Key Attributes
� �

Non Volatility Flexibility


No Erase, Bit alterable, Continuous Writing

Attributes
Non-Volatile Scaling Granularity Erase

PCM
Yes sub-2x nm Small/Byte No Easy ~Flash 1- 15+ MB/s

EEPROM
Yes n.a. Small/Byte No Easy ~Flash 13-30 KB/s 200-200 ns 105 -106

NOR
Yes 3x nm Large Yes Moderate ~Flash 0.5-2 MB/s 70-100 ns 105

NAND
Yes 2x nm Large Yes Hard ~Flash 10+ MB/s 15 - 50 us 104-5

DRAM
No 3x nm Small/Byte No Easy High 100+ MB/s 20 - 80 ns Unlimited

� � � � �

Lower power consumption than RAM Fast Writes Read bandwidth and writing throughput eXecution in Place Extended endurance

Software Power Write Bandwidth

Read Latency Endurance

50 - 100 ns 106+

PCM provides an new set of features combining components of NVM with DRAM
11 September 2011 �2011 Micron Technology, Inc. | 12

Ultimate Scalability of PCM

Y. C. Chen et al., IEDM 2006 P.Wong, EPCOS 2010

� � �

Device functionality demonstrated on 60 nm2 active area Reset current
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