Today's nanometer-scale Integrated Circuits (ICís) call for extensive changes in all facets of the design flow. The need for advanced interconnects and packages have become more critical. Mechanical issues and contact probing restrictions prevent testing during 3D multi-chip assembly process.
IC assembly and packaging flows are susceptible to yield excursions. Enabling a new level chip-scale integration for the semiconductor industry. Complex SiP designs presently are not cost-effective.