SRC GRC University Research Highlights Feb 08

SRC GRC University Research Highlights Feb 08

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Author: Dale Edwards, William Joyner, Kwok Ng, David Yeh, Scott List, Dan Herr (Fellow) | Visits: 1494 | Page Views: 1496
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Maxims of Tech: Rules of Engagement for a Fast Changing Environment
Research Highlights for the February 2008

Computer Aided Design & Test Sciences
Technical Thrust: Logic & Physical Design Research Highlight: Circuit Simulation Engine for Variation and Electrical-Aware OPC/RET Insertion This report summarizes work on dealing with systematic variation in device parameters by understanding the variability mechanism and modeling impact of process variations on circuit performance. Parametric variation in general and systematic variation in particular is being projected as a major yield limiter in sub-65nm technologies. The first part of the work develops various simulation models to describe process variations and their impact on device properties. The four major sources of systematic variation modeled are lithography, stress, etch and contact resistance. In the second part of the work the researchers implement a circuit simulator for 45nm SOI devices which examines the effect of layout-dependent systematic variations on circuit delay and power. Results highlight the need to integrate such models into the current design flow for accuracy of timing sign-off. Univ. of Texas/Austin SRC Contact: W. Dale Edwards ( Research Highlight: Faster Power Grid Verification Using a Current-Sampling Approach In deep sub-micron (DSM) technologies, with reduced supply voltage levels, chip designs are becoming increasingly susceptible to supply voltage problems. Proper analysis and verification of the power grid are required for reliable high-performance and high-density chip design. In previous work under this project, the researchers had tackled the grid verification problem as an optimization problem in the voltage space. More recently, the problem was transformed and solved (with much improved efficiency) as a sampling/search problem in the current space, as was presented at the last annual review. This report provides the full details of this reformulation and includes (after a brief 2-page introduction) the paper that was presented on this at ICCAD-07. Univ. of Toronto SRC Contact: W. Dale Edwards ( Research Highlight: Report on the Design Techniques for On-chip Test Structures for Post-silicon Tuning Circuits built in deeply scaled nanometer technologies are strongly susceptible to process and environmental variations. These effects can cause manufactured circuits to drift from their designed specifications, causing variation-induced yield losses that have potentially severe economic consequences. Such variations have major implications on next-generation design tools and methodologies, and fundamental changes are necessary from the techniques used to analyze and optimize circuit performance metrics today. Much research has been carried out in the important area of statistically-conscious design, providing a firm theoretical backing for industrial progress on that front. This research addresses the complimentary area of developing GRC is a program of Semiconductor Research Corporation P.O. Box 12053, Research Triangle Park, NC 27709

statistically-based techniques for post-silicon tuning and diagnosis of manufactured die. Univ. of Minnesota SRC Contact: W. Dale Edwards ( Technical Thrust: Test and Testability Research Highlight: Report on the Data Collection and Report Benchmark Statistical Analysis of Data This research task seeks a statistical model response to systematic and parametric variation of semiconductor designs through changes in the test flow and changes in the test content. Model performance will be measured in three ways; 1) test time reduction, 2) pattern volume requirements, and 3) outgoing quality predictors. Random defect testing and parametric variation pose significantly different test problems. Parametric variation is projected to be the dominant failure. Transition delay is the dominant parametric test. To achieve acceptable coverage levels TDF requires large ATE pattern volumes, external or internal support for at-speed clocks or TDF requires circuitry supporting Built-In-Self-Test. BIST leverages the faster internal circuitry for fast pattern execution but measuring BIST TDF fault coverage remains a research challenge. Portland State University SRC Contact: William H. Joyner ( Research Highlight: Report on the Data Collection and Report Benchmark Statistical Analysis of Data The research task seeks a statistical model response to systematic and parametric variation of semiconductor designs through changes in the test flow and changes in the test content. Model performance will be measured in three ways; 1) test time reduction, 2) pattern volume requirements, and 3) outgoing quality predictors. Random defect testing and parametric variation pose significantly different test problems. Parametric variation is projected to be the dominant failure. Transition delay is the dominant parametric test. To achieve acceptable coverage levels TDF requires large ATE pattern volumes, external or internal support for at-speed clocks or TDF requires circuitry supporting Built-In-Self-Test. BIST leverages the faster internal circuitry for fast pattern execution but measuring BIST TDF fault coverage remains a research challenge. Portland State University SRC Contact: William H. Joyner ( Research Highlight: Diagnosis for Performance Failures Considering Realistic Noise, Process Variations, and Defects The research team developed a range of techniques for detection and diagnosis of performance failures considering realistic noise, process variations, and defects. In particular, the team developed the first approach for diagnostic reasoning that considers weak-resistive bridges, which have recently emerged as a dominant failure mode in nano-scale CMOS circuits and are growing in importance with each generation of fabrication process. A weak-resistive bridge, or a WRB, is a bridge whose resistance is sufficiently high so as to not cause static errors yet sufficiently low to cause timing errors. The researchers also developed the first suite of procedures for generating tests (pairs of patterns) that detect and/or improve the diagnostic

resolution for a range of combinations of delay induced anomalies usually caused by process variations and defects, such as crosstalk and WRBs. Univ. of Southern California SRC Contact: William H. Joyner ( Research Highlight: A Study of the Detection of Faults Internal to Scan Cells This study was initiated to improve defect coverage in large industrial designs using structural tests. Typical approaches taken to improve defect coverage is to enhance test suites to detect additional fault types or use n-detection tests for existing fault models such as single line stuck-at faults. The approach being taking is to first identify the test holes and develop methods to generate tests to detect the faults not covered by existing test methods. The authors decided to investigate faults internal to scan cells that are not directly targeted by existing tests. The researchers are using a large industrial design for this study and the current status of this study and results obtained up to now are summarized in this report. This report has three parts. The first part is an executive summary that gives an overview of the test problem investigated and two appendices that give details. Appendix I is a paper to be presented at VLSI Test Symposium in April 2008 and Appendix II is a paper submitted to the 2008 International Test Conference. Univ. of Iowa SRC Contact: William H. Joyner ( Technical Thrust: Verification Research Highlight: Final Report Summarizing Research Accomplishments on Formal Verification of High-Level Models and Transformations Between Them In the first year of this task, the researchers focused on applying the translation validation method to provide automatic proofs for backward compatibility of microcode. The work was done in collaboration of the DT group at Intel, Israel. To continue their task, it was necessary to obtain some software from Intel. During the second year of the task, it became clear that for reasons that were beyond the control of the participants in the task, the software cannot be made available to them. Consequently, while they focused their efforts that year on issues that may be applicable to the original task, however, this was done without clear guidance from SRC. Then, they re-defined their task to one that, while still retaining the spirit of verification of a low-level implementation satisfying its higher-level specifications, applies this reasoning to transactional memory rather than microcode. Univ. of Illinois/Chicago SRC Contact: William H. Joyner (

Device Sciences
Technical Thrust: Device Sciences Modeling & Simulation

Research Highlight: Continuum Models for Boron Diffusion/Clustering During/Following SPER Continuum models for boron diffusion in amorphous silicon have been developed and implemented. They account for the experimental observation of time and concentration dependent diffusivity by considering different site energies for substitutional B in amorphous Si. The resulting models describe the boron diffusion kinetics during regrowth in amorphous silicon preamorphized by germanium or silicon ion implantation. The models are characterized by comparison to experimental data. Univ. of Washington SRC Contact: Kwok Ng ( Research Highlight: Boron Diffusion in Amorphous Silicon-Germanium Alloys The effect of Ge alloying on B diffusion in amorphous Si(1-x)Ge(x) alloys is reported for x = 0 0.24. The diffusivity is observed to decrease with increasing Ge concentration despite an increase in the activation energy for B diffusion, which ranges from 2.8 eV for amorphous Si to 3.6 eV for amorphous Si(0.76)Ge(0.24). This is in sharp contrast to results for amorphous Ge where an increase in diffusivity of 4 orders of magnitude relative to amorphous Si is observed. It is suggested that Ge distorts the amorphous Si network thereby increasing B trapping by Si. Univ. of Florida SRC Contact: Kwok Ng ( Research Highlight: Report on the Calculation of Effect of Tensor Stress on Energy of Climb/Glide Transitions Dislocation formation and evolution is important to understand in modern nanoscale CMOS processes because of the potentially adverse effects on device performance and reliability. Dislocations grow by incorporating atoms at the core and move via so-called glide and climb mechanisms. In order to better understand the evolution of these defects, the transition states for these processes have been investigated with ab-initio calculations. Univ. of Washington SRC Contact: Kwok Ng ( Research Highlight: Report on the Calculations and Resulting Continuum Models for Diffusion of B, As, and P in Si:C and Si:Ge:C DFT calculations of the interactions of C and Ge with dopant species in Si:C and Si:C:Ge enables the development of continuum models for the dopant diffusion in strained group IV alloys as function of alloy composition. Univ. of Washington SRC Contact: Kwok Ng ( Technical Thrust: Digital CMOS Research Highlight: Materials Development for Low Resistance Contacts

The main objective of this proposal is to guide the experimental development of new low barrier alloys for source/drain contacts in ultra-scaled CMOS by providing a fundamental understanding of the structure-property relations between the crystal structure, chemical composition and atomic structure of the alloy/semiconductor interface on one hand and the SBH on the other hand. The researcher?s theoretical work is meant to support the Ultimate CMOS Center and others funded by the SRC. Complex phase landscape and unclear correlation between the stoichiometry and structure with the SBH render theoretical modeling exceptionally useful. Density functional theory (DFT) offers a unified systematic approach to evaluating metallic alloys for low Schottky barrier contacts. This year they have investigated two problems. First they studied the optical properties and bonding in PtSi (in collaboration with Drs. S. Zollner and R. Gregory of Freescale Semiconductor), and second, they considered possible ways of improving its conductivity by doping. Univ. of Texas/Austin SRC Contact: Kwok Ng ( Research Highlight: Report on Films and Device Models Compared to the traditional Si or SiGe MOSFET, III-V MOSFET usually exhibits higher speed and consumes lower power. Among various III-V material, InGaAs/InP is chosen because this material system exhibits good electron mobility and large conduction band discontinuity to confine 2DEG electron. Since III-V material does not have high quality native oxide, the quality of interface trap charge will play a key role on the MOSFET behavior. The achievement at the year of 2007 is to characterize and optimize the interface trap charge between high-k dielectric and III-V surface. The samples prepared for the characterization are InGaAs and InAlAs films grown separately on InP substrate. Both films are lightly n-doped and lattice matched to the InP. MOS capacitance devices are then fabricated and characterized on these samples. Univ. of Michigan SRC Contact: Kwok Ng ( Research Highlight: Measurement of the Floating Body Effects of 65nm PD SOI CMOS Devices Considering the STI Mechanical Stress This report summarizes the experimental measurement of the shallow trench isolation (STI)induced mechanical stress-related kink effect behaviors of the 40nm PD SOI NMOS device. As shown in the measured data and verified by the 2D simulation results, the kink effect behaviors occur at a higher VD in the saturation region and show a less steep subthreshold slope for the 40nm PD device with a smaller S/D length of 0.17�m due to the weaker function of the parasitic bipolar device as a result of the larger body-source bandgap narrowing (BGN) effect coming from the higher STI-induced mechanical stress. National Taiwan University SRC Contact: Kwok Ng (

Integrated Circuits & Systems Sciences
Technical Thrust: Circuit Design

Research Highlight: Gselect Gselect is a tool to select FinFET cells in a combinational circuit. It can minimize total power consumption under a delay constraint. The library description file lists all available .lib files, one file per line. The following finfet libraries are included sg.lib - shorted gate FinFET cells. lp.lib back gates reverse-biased. ig.lib - Cells with parallel transistors merged into a single FinFET. iglp.lib - The software processes edif netlists that might represent initial mapping. Activity description provided in the form of a .saif file is required. Princeton University SRC Contact: W. Dale Edwards ( Research Highlight: TCMS_buf The software can place and insert buffers on a wire net. A listing of buffers placed on each location and area, delay and power estimates is generated. Princeton University SRC Contact: W. Dale Edwards ( Research Highlight: Design Techniques for High-PSRR VCOs and PLLs This report summarizes new design techniques to implement phase-locked loops with excellent power-supply noise rejection properties. In particular, a supply-regulated phase-locked loop (PLL) that employs a split-tuned oscillator and a replica-feedback regulator to decouple the tradeoff between supply-noise rejection performance and power consumption is presented. The prototype PLL, fabricated in a 0.18um digital CMOS process, operates from 0.5 to 2.5GHz and achieves a worst-case supply noise sensitivity of -28dB (50fs/mV at 1.5GHz), an improvement of 22dB over the conventional regulated PLL. Operating at 1.5GHz, the PLL consumes 3.9mW, and achieves a measured peak-to-peak jitter of 15ps with no supply noise and 25ps with a 200mVpk-pk sinusoidal noise. This architecture is also very amenable to digital phase-locked loops. Oregon State University SRC Contact: W. Dale Edwards ( Research Highlight: WCDMA Integrated Transmitter Technology Transfer Report The purpose of this document is to present the final design and evaluation results of a WCDMA transmitter designed in a 90 nm CMOS process. The overall project goal of demonstrating the potential for 90nm CMOS to perform comparably with SiGe BiCMOS for high performance cellular applications was achieved. The primary goal of the final design is to meet the linearity and output power requirements of the WCDMA transmitter specifications while incorporating 54 dB of RF gain control. The transmitter produces +9.0 dBm output power with -43.2dBc ACLR@5Mhz and 9% power efficiency. This report is a summary of the initial assessment of the performance of the transmitter design. North Carolina State University SRC Contact: W. Dale Edwards (

Research Highlight: Design of a High Power, High Bandwidth Drain Modulator, with Target Specifications Peak Power 200W, Bandwidth 50MHz and Efficiency >80% Drain modulators are key components for the implementation of drain modulation RF amplifiers, which employ time-varying power supply voltage in order to improve their power efficiency. This report summarizes the design at UCSD of a novel drain modulator that extends the capabilities of previous modulators, increasing the voltage range of operation from 32V to 4550V while maintaining a high maximum power level. Design considerations and experimental results are provided for the linear stage of the drain modulator and for its switching stage. Univ. of California/San Diego SRC Contact: W. Dale Edwards ( Research Highlight: Final Report Summarizing Research Accomplishments on System Embedded Calibration of A/D Converters This report summarizes the accomplishments of this task. The authors have demonstrated the design of an A/D converter that employs an energy-efficient SAR architecture together with a digital background calibration algorithm tailored to OFDM receivers. The distinguishing features of the proposed calibration scheme lie in the reuse of digital system resources and the exploitation of redundant features (pilot tones) in the received signal. An experimental 6-bit prototype ADC was fabricated in 0.18-um CMOS technology and tested within the OFDM system environment. At a sampling rate of 200 MS/s, the ADC achieves an SNDR of 35.4 dB with a total power dissipation of 6.58 mW. The proposed calibration yields an SNDR improvement of 20 dB after a convergence time of 10(8) clock cycles. Stanford University SRC Contact: W. Dale Edwards (

Technical Thrust: Integrated System Design Research Highlight: Report on Micro-Architecture Synthesis Algorithm and Prototype Tools for RF Interconnect Given the pin locations for system level interconnects, micro-architecture synthesis of system level interconnects decide which division scheme, i.e., either time-division or code-division multiple access to be used. The key is to build high abstraction level models for such schemes. While the time-division multiple access is the commonly used bus structure with buffered interconnects and known cost, this report proposes parameterized models for code-division multiple access (CDMA) RF interconnects. The researchers also point out that the analog component in the CDMA interconnects limits the application of CDMA interconnects for smallscale interconnects. This is one of motivations for a new project "Crosstalk Insensitive Electrical Signaling for Wired Data Communications" which develops CDMA interconnect with simplified analog components and also extends synthesis of system level interconnects with CDMA schemes. Univ. of California/Los Angeles

SRC Contact: David C. Yeh ( Research Highlight: Strategies and Preliminary Results from Integrating Tunneling-based Nondifferentiable Optimizers into Global Optimizer Frameworks Report describing strategies and preliminary results from integrating tunneling-based nondifferentiable optimizers into existing stochastic global optimizer frameworks. Carnegie Mellon University SRC Contact: David C. Yeh ( Research Highlight: Report to Analyze Communication Architecture Power Consumption under PVT Variations This report investigates the impact of PVT corners (and variation) on power consumption at the System-on-Chip (SoC) level, especially for the on-chip communication infrastructure, as part of our Power Optimization Framework for SoCs. Given a target technology library, the authors then show how it is possible to "scale up" and abstract the PVT variability at the system level, allowing characterization of the PVT-aware design space early in the design flow. This allows the team to obtain more reliable and PVT-aware power estimation early in the design flow for the interconnect fabric, as part of our system level power-performance trade-off communication architecture synthesis framework that was described in the previous reports. The rest of the report presents results of the analysis of power consumption under PVT variations, and then presents preliminary results on the accuracy and speedup of scaling technique-based approach for system-level PVT-aware power estimation of communication architectures. Univ. of California/Irvine SRC Contact: David C. Yeh (

Interconnect and Packaging Sciences
Technical Thrust: Back End Processes Research Highlight: Report on Compressive Failures in Cu/Low-k Interconnect Trees Low-k dielectrics have low mechanical stiffness and are more susceptible to failure due to electromigration-induced extrusions of Cu. The researchers have performed EM experiments under conditions that favor extrusion failures, to analyze the EM-induced stress required to cause this failure mechanism and to understand the effects of materials and layout properties. The critical stress for extrusion-failure is of order 100MPa. However, the magnitude of the critical stress depends on the adhesive strength of the interface between the low-k dielectric and the inter-level diffusion barrier, and on the Cu pattern density. Mass. Institute of Technology SRC Contact: R. Scott List ( Research Highlight: Report on Preparations of New Low-k Films, Including Experimental Parameters and Characteristics of the Resulting Low-k Films

With the dimension of devices decreasing in ultra large-scale integrated circuits, the propagated delay caused by interconnects increases rapidly. To reduce resistance-capacitance delay, various low-dielectric-constant (low-k) materials have been researched as inter-metal dielectrics by reducing the parasitical capacitance. SiOC(-H) is receiving more attention as a promising low-k dielectric material for applications to advanced copper interconnects due to its lower dielectric constant, better thermomechanical properties, and lower adsorption coefficients for moisture. However, the incorporation of amorphous carbon or C(n)H(x) groups will cause a decrease in mechanical strength of the deposited film. Recently, Peng et al have reported that NH(3) plasma surface treatment can improve the mechanical properties of the low-k MSQ film without increasing markedly its dielectric constant. Furthermore, Fainer et al also suggest that the Si-C-N films have large microhardness, high Young's modulus, and a wide dielectric constant range of 3.0-7.0. Therefore, it is significant to explore incorporation of carbon and nitrogen in the conventional SiO(2) inter-metal dielectric (i.e., SiOCN dielectric) to achieve a low k value, at the same time, it is expected that the SiOCN films have enough hardness and Young's modulus. In the present report, low-dielectric-constant (low-k) carbon- and nitrogen-doped silicon oxide (SiCON) films are deposited by plasma-enhanced chemical vapor deposition (PECVD) using a mixture of SiH(4), N(2)O and C(2)F(6). The experimental results indicate that the k value decreases with reducing the flow rate ratio of N(2)O/C(2)F(6) and increasing the RF power, respectively. This is attributed to incorporation of more carbon and less nitrogen atoms. Furthermore, it is revealed that the deposited SiCON films contains multiform bonding states such as Si-C, Si-N, C(sp3)-N, C(sp3)-C(sp3), C(sp2)=N, N-O and C-O bonds, and a high RF power increases markedly the relative concentration of cross-linked C-C bonding state. Further, the team investigated the influence of RF powers on the electrical properties of the deposited SiCON films for the constant other deposition parameters (150sccm N(2)O, 150sccm SiH(4), 300sccm C(2)F(6); 200 degrees C substrate temperature). It is revealed that the resulting dielectric constant decreases from 3.51 to 2.33 with increasing the RF power from 1.1kW to 1.8kW. Meanwhile, the deposited films exhibit low leakage current densities. As for the film with a dielectric constant of 2.33, the leakage current density equals ~3 times 10(9)A/cm(2)@1MV/cm. Fudan University SRC Contact: R. Scott List (

Technical Thrust: Packaging Research Highlight: Report on the Verification of 5 GHz I/O Test ICs This research program develops and characterizes Giga-bit-per second (Gb/s) differential and single-ended I/O interface test ICs for high-speed I/O chip-to-package-to-board interface evaluation and modeling verification. A single-ended 5 GHz signal bandwidth Gunning Transceiver Logic (GTL) I/O test system was designed and fabricated in TI 65 nm CMOS in Jan. 2007 and March 2007 runs. Tests of the individual ICs and boards using this IC show that the IC launches 78 ps risetime (4.7 GHz knee frequency) transients that are degraded through board wires, traces and crosstalk. Near-end crosstalk (NEXT) and far-end crosstalk (FEXT) are measured and modeled.

Univ. of Florida SRC Contact: R. Scott List ( Research Highlight: Mechanical Behavior and Microstructure Evolution of SnAgCu and SnAgCu-RE Pb-free Solders Pb-free solders pose new problems and challenges associated with their incorporation into electronic components. Recently, a new class of Pb-free solders has been discovered, with preliminary properties that appear to be superior to that of Sn-rich alloys based on Cu and Ag. The new alloys contain a very small fraction of a rare-earth (RE) element. A fundamental understanding of the microstructure of these alloys is very important to the semiconductor industry (ITRS Grand Challenge #8). In this deliverable report the researchers examine in detail the microstructure and various properties of this novel class of materials containing La, Ce, and Y. Arizona State University SRC Contact: R. Scott List ( Research Highlight: Report on Design and Process Flow of Hermetic/Vacuum Packaging of MEMS Device The purpose of this task is to design, develop, build and test a novel, wafer-level packaging technique for MEMS devices. This report summarizes the successful fabrication of MEMS resonators with a high Q factor and a vacuum-packaged cavity without the resonators. The resonators without the package demonstrated a relatively low pull-down voltage and a high Q factor. Vacuum cavity packages fabricated without the resonators survived the overmolding process at a member company. Since the Q-factor of the resonator depends upon the vacuum pressure, emphasis has been given to the device-level vacuum packaging for RF MEMS devices. A two-sacrificial layer self-packaged MEMS resonator was designed and successfully fabricated. Univ. of Texas/Arlington SRC Contact: R. Scott List ( Research Highlight: Development of Thermo-Electric-Mechanical Fatigue Model for Solder Joint Incorporating Constitutive Model for Intermetallics The research team conducts research on electromigration effect on interconnect failure and include discussions on failure of IMC in solder/Cu pad interface for flip-chips during this contract year. Current research is focused on the behavior of solder and IMC behavior under thermal-mechanical cyclic load. Northwestern University SRC Contact: R. Scott List ( Research Highlight: CTE, Elastic Properties and Hardness of Sn-containing Intermetallics in Modern Solder Interconnects Ambient-temperature isotropic elastic moduli (bulk, Young's, shear, and Poisson's ratio) and hardness (Vickers) are re-measured for the following Sn-containing intermetallics: Ag(3)Sn, AuSn(4), AuSn(2), AuSn, Cu(3)Sn, (Cu(1-x)Ni(x))(6)Sn(5), (Ni(1-x)Cu(x))(3)Sn(4), PdSn(4)

and PdSn(3). The coefficient of thermal expansion of most of these intermetallics are measured by dilatometry. Single-crystal elastic constants of binary intermetallics are calculated (at 0 K) from first-principles employing density functional theory. These along with their polycrystalline averages are reported. The calculated polycrystalline elastic moduli are compared with experimental data. One or more of these intermetalllics are present in modern solder interconnects; therefore, their mechanical and thermo-physical properties are important in micromechanical modeling of failure prediction of solder joints. Northwestern University SRC Contact: R. Scott List ( Research Highlight: ABAQUS Input File and UCP Subroutine Code for Solder/IMC Interconnect A 3D finite element model using ABAQUS is developed to predict the crack nucleation, propagation and solder/IMC interfacial damage of interconnects. Unified creep-plasticity theory is incorporated in the model to predict the creep and hysteresis effects in solder. Cohesive zone model is adapted to predict the interfacial behavior between the solder bulk and the intermetallic layer. Northwestern University SRC Contact: R. Scott List (

Nanomanufactuing Sciences
Technical Thrust: Patterning Research Highlight: Incorporation of Multi-functional Octasilsesquioxane - Based Materials and Evaluation of the Effects of Additive/Resist Interaction Strength on Resist Properties Progress is reported on increasing the density and glass transition temperature and reducing chain and acid mobility in resist formulations through the addition of nanoparticles and other multi-functional additives that exhibit strong interactions with the resist chain segments (poly(4hydroxystyrene) (PHOST) based at present). The dispersion, blend compatibility, density and Tg of blends of functionalized polyhedral oligomeric silsesquioxanes (POSS) compounds and molecular glasses including alpha,alpha,alpha'-Tris(4-hydroxyphenyl)-1-ethyl-4isopropylbenzene (MG2OH) with PHOST were evaluated. The model molecular glass component was shown to be well dispersed in the resists while the POSS additives were not. The molecular glass results guided the synthesis of new multi-functional resist additives including those that can be protected and de-protected using photoacids with the objective of improving resist resolution. Univ. of Massachusetts SRC Contact: Daniel J. C. Herr ( Research Highlight: Final Report Summarizing Research Accomplishments on Materials

and Processes for Sub-32 nm Lithography This final report summarizes research accomplishments and future direction for materials and processes for sub-32 nm lithography. Univ. of Wisconsin/Madison SRC Contact: Daniel J. C. Herr ( Research Highlight: Design Consderations for an Azimuthally (TE) Polarized Condenser for DUV Wavelengths This report summarizes the progress to date in the design and construction of illuminator elements equipped to provide efficient, azimuthally polarized ring illumination. The design combines an optimized toric focusing element with a stress-engineered window to efficiently convert linearly polarized illumination to azimuthal (TE) illumination. Univ. of Rochester SRC Contact: Daniel J. C. Herr ( Research Highlight: Report on Lithographic Properties of Block Copolymer Directed Assembly The researchers report on the rapid directed assembly of polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) block copolymer thin films at elevated temperatures on chemically patterned surfaces. The time needed for defect free assembly, where the chemical pattern (LS) closely matches the natural length of the block copolymer (L0), is strongly dependant on the annealing temperature (150 minutes at 180 C to 3 minutes at 230 C). This system behavior is well described as a thermally activated process. Modeling this behavior predicts assembly times of 13.5 seconds at 250C and 1.9 seconds at 280 C. Experimental assembly was realized at T > 250 C in less than 1 minute. Univ. of Wisconsin/Madison SRC Contact: Daniel J. C. Herr ( Research Highlight: Report on Synthesis and Assembly of Functionalized Block Copolymers The researchers investigate the assembly of block copolymer/nanoparticle composite films on chemically nanopatterned substrates and present fully three-dimensional simulations of a coarse grain model for these hybrid systems. The location and distribution of nanoparticles within the ordered block copolymer domains depends on the thermodynamic state of the composite in equilibrium with the surface. Hierarchical assembly of nanoparticles enables applications in which the ability to precisely control their locations within periodic and non-regular geometry patterns and arrays is required. Univ. of Wisconsin/Madison SRC Contact: Daniel J. C. Herr ( Research Highlight: Report on the Directed Assembly of Three Dimensional Structures using Triblock Copolymers

The use of the triblock copolymer in lithography has many advantages over the diblock. With promising experimental results of triblock copolymer using poly(isoprene-b-styrene-bethylene oxide) (PISO) directed to assembly over a chemical surface pattern, use of simulations in predicting the behavior in thin film patterns is a active area of research. The advantage of simulations is that various types of the polymers can be used to predict the behavior in a short time by changing their interaction parameters of the blocks. Univ. of Wisconsin/Madison SRC Contact: Daniel J. C. Herr ( Research Highlight: Report on Progress for Reduction of LER by Reflow at 19nm Line Edge Roughness (LER) is a major problem for the 22nm lithography node and beyond. The SIA has identified LER as the major challenge in EUV lithography. In addition to study the causes of the formation of LER, The researchers have also investigated the possibility of reducing LER by surface reflow. The hypothesis is based on two observations. First, after development the resist surface is in a state of high surface energy, because of the rough nature caused by the LER. Second, it is well known that the glass transition temperature at the surface is lower than that of the bulk. Thus, it should be possible to reflow the surface without affecting the bulk of the photoresist, thus smoothing out the LER. The team has been partially successful in this. In experiments on Chemically Amplified Resists, the authors have decreased the LER by 40-50%. While this is significant, it is less of what was hoped for. Univ. of Wisconsin/Madison SRC Contact: Daniel J. C. Herr ( Research Highlight: Report on Progress of Energy Flow Simulation for Ultra-small Features The goal of this task is the development of a complete the image formation suite for high-energy lithographies. The research team has developed a very extensive dose image formation model based on a Monte Carlo (MC) simulation of the cascade of interactions created by electrons moving through the photoresist. In contrast to other approaches, the authors include detailed and accurate simulation of the scattering processes, and explicitly follow the energy deposition process in the material from an atomic and molecular point of view. In other words, given a material of a certain composition the team can predict which atoms will be excited by the hot electrons created either by an external beam (electron beam lithography) or by an internal process (EUV or XRL). The MC further can predict the localization of the acid, and thus provide the input to dissolution models for the estimation of the LER. Univ. of Wisconsin/Madison SRC Contact: Daniel J. C. Herr ( Research Highlight: Final Report Summarizing Research Accomplishments on Image Formation and Metrology for Sub-32nm Lithography The overall goal of this task is to extend the predictive modeling capabilities to include lowenergy electrons (as found in EUV), detailed local sources of LER, non-uniform acid distribution (depletion). The modeling is complemented by experimental verification; the team has explored

the reduction of LER with reflow techniques, and their impact on CD variation and uniformity. The first part of the activity (modeling) has progressed to the point that the code is almost ready for technology transfer. As part of the modeling effort, the researchers have developed a comprehensive model for the understanding of the details of the image formation in EUV interferometric and holographic lithography. The second part (reflow) has shown limited success, and will not been continued as part of this task. Future directions involve a push on EUV Interferometric Lithography, the only method currently capable of delivering routinely 20nm half-pitch lines in the EUV. The authors have a world-class EUV Interferometer, developed with funding from NSF and Sematech, that will be used for this project. It is planned to use EUV-IL to explore the effect of flare on LER in EUV Lithography. Univ. of Wisconsin/Madison SRC Contact: Daniel J. C. Herr ( Research Highlight: Image Formation and Metrology for Sub-32nm Lithography The proposed work under Task 4 was built on the premise that the engineering, physics and chemistry of sub-30nm photoresist structures are fundamentally different from those relevant at longer lengths scales. An individual photoresist molecule can measure 5 to 10 nm, and the system of interest (e.g. a nanoscopic feature) can no-longer be treated as a macroscopic continuum. Work over the duration of contract 985 from SRC established unequivocally that the thermophysical properties of photoresist materials in nanoscopic structures are considerably different from those of the same materials in the bulk. This work also established that, particularly for amorphous materials (such as photoresists above and below the glass transition), continuum treatments simply breakdown at nanometer length scales. Perhaps more importantly, the work identified two strategies to reduce or eliminate the observed size dependence of mechanical properties in ultra-small photoresist structures. The research conducted under Task 4 of contract 985 led to 24 publications in some of the most highly regarded scientific journals, including Physical Review Letters, Science, and many others. The research performed by de Pablo and co-workers has also attained over an unprecedented 900 citations per year. This level of accomplishment might very well make Task 4 's research the highest-impact in all of SRC materials portfolio, all of it at a relatively modest level of investment. The authors also note that Task 4's relevance to emerging challenges in the semiconductor industry and Task 4's success in meeting those challenges have consistently been praised by SRC-member companies throughout every one of the annual reviews. Univ. of Wisconsin/Madison SRC Contact: Daniel J. C. Herr ( Research Highlight: Report on EUV Generation Optimization with a Fiber Laser Driver The project addresses ITRS Grand challenge 7 EUVL (Extreme Ultraviolet Lithography). This report summarizes recent experimental results of demonstrating and characterizing efficient 13.4nm EUV generation from a mass-limited Sn-doped droplet source irradiated by a fiber laser driver, which have been conducted in collaboration with Professor Richardson's group at the University of Central Florida (droplet target source). The researchers had shown that a properly designed fiber laser driver can provide with optimal hot-plasma conditions leading to 2% in-band EUV conversion efficiency, the same as the efficiencies achievable with conventional solid-state

laser sources. Fiber laser driver operation conditions are advantageously different from a pulsed solid-state laser operation in that fiber laser permits high repetition rate (20kHz - > 80kHz) operation with electronically adjustable pulse shape, controllable pre-pulse generation and very high optical beam quality. This validates feasibility of using fiber lasers as drivers for LPP EUV sources, which potentially can provide highly economical approach to EUV lithography. Univ. of Michigan SRC Contact: Daniel J. C. Herr (